Simulation Analysis and Characterization of Low Power and High-Speed Digital Circuits

Power consumption and delay are two important considerations for VLSI systems which depend on various critical design parameters. The objective of this project is to reduce the power and to reduce the delay which increases the speed. The purpose of this paper is the design and implementation of an Arithmetic Logic Unit (ALU) using area optimizing techniques such as Gate Diffusion Input (GDI). In this paper, a high speed full adder simulated using improved Gate Diffusion Input (GDI) technique. We further implement it in 4-bit arithmetic logic circuit (ALU) by the concept of Gate Diffusion Input (GDI) technique. In this ALU consists of full adder designed to number of functional units for different arithmetic and logic operations, such as AND, OR, etc. and arithmetic operations, as ADD and SUBTRACT. The Tanner EDA simulation shows that the design proposed ALU is better than CMOS ALU around the power savings was between 20 to 50%. The proposed ALU shows that it is better than CMOS ALU in terms of speed, power and power delay product